1. Field of the Invention
The present invention relates to a capacitive flat matrix display device, and specifically to an inorganic EL (electroluminescence) display device including a plurality of light emitting layers having different light emission characteristics.
2. Description of the Related Art
A display panel of an inorganic EL display device includes a substrate, and a plurality of strip-like first electrodes (data-side electrodes) and a plurality of strip-like second electrodes (scanning-side electrodes) provided on the substrate. The plurality of first electrodes are arranged in parallel to each other, and the plurality of second electrodes are arranged in parallel to each other. The plurality of first electrodes and the plurality of second electrodes are arranged so as to be perpendicular to each other. At each of intersections of the first electrodes and the second electrodes, an inorganic EL element is provided. Each inorganic EL element includes three stacking layers, i.e., an insulating layer formed of a dielectric material, a light emitting layer, and an insulating layer formed of a dielectric material. The inorganic EL elements are provided in a matrix, each acting as a display dot. The display panel includes a plurality of types of light emitting layers so that the color can be changed. An inorganic EL element has the applied voltage vs. luminance characteristics as shown in FIG. 7. The inorganic EL element is driven at a relatively high voltage of about 200 V.
A conventional inorganic EL display device includes a scanning-side driving circuit of a push-pull structure, which includes an output element for applying a negative voltage and an output element for applying a positive voltage both to the scanning-side electrodes. The conventional inorganic EL display device also includes a data-side driving circuit including a source follower-type output element for charging the light emitting layers with a modulation voltage.
The data-side driving circuit uses the charging output element and a discharging output element so as to perform modulation driving. By the modulation driving, the inorganic EL element is charged and discharged in accordance with a display data signal until a modulation voltage of an arbitrary amplitude is obtained. The scanning-side driving circuit uses a switching element such as, for example, a thyristor, so as to perform so-called field inversion driving. Thus, an AC pulse having high symmetry is applied to the light emitting layers, resulting in highly reliable display.
A specific structure of an inorganic EL display device 1000 will be described with reference to FIG. 1. In this example, eight-grade display is provided.
The inorganic EL display device 1000 shown in FIG. 1 includes an EL display panel 106. The EL display panel 106 includes data-side electrodes X1a, X1b, . . . , Xna and Xnb, and scanning-side electrodes Y1, Y2, . . . , Ym. The data-side electrodes and the scanning-side electrodes are perpendicular to each other. At each of intersections of the data-side electrodes and the scanning-side electrodes, a light emitting layer A or a light emitting layer B is provided in the state of being interposed between two insulating layers. The light emitting layer A has the voltage vs. luminance characteristic shown in FIG. 7 (labeled as “light emitting layer A”), and has a light emitting threshold voltage of VWa and a light emitting saturation voltage of VSa. The light emitting layer B has the voltage vs. luminance characteristic shown in FIG. 7 (labeled as “light emitting layer B”), and has a light emitting threshold voltage of VWb and a light emitting saturation voltage of VSb. The light emitting layer A or the light emitting layer B and two insulating layers interposing the respective light emitting layer act as a display dot. As shown in FIG. 1, a display dot including the light emitting layer A and a display dot including the light emitting layer B are arranged alternately in an M direction. A pixel includes a pair of display dots of these two types.
A driving control circuit 101 is provided in the vicinity of the EL display panel 106. The driving control circuit 101 receives external signals including a vertical synchronous signal VS, a horizontal synchronous signal HS, a data transfer clock signal CKD, and display data signals D0 through D2. The display data signals D0 through D2 exhibit eight grades of luminance. Table 1 shows the relationship between the display data signals D0 through D2 and the luminance. In Table 1, L0 represents the lowest luminance and L7 represents the highest luminance.
TABLE 1LuminanceD2D1D0BrightestL7HHH.L6HHL.L5HLH.L4HLL.L3LHH.L2LHL.L1LLHDarkestL0LLL
The driving control circuit 101 is operated by a logic circuit voltage VL (e.g., 5 V) which is externally input to the driving control circuit 101.
The driving control circuit 101 generates the following control signals in order to control an operating timing of each of a plurality of portions of the EL display device 1000 in accordance with the input signal. A PN frame signal PNF controls a first frame and a second frame of a display frame. The PN frame signal PNF is “H” in the first frame and is “L” in the second frame. A ramp wave output signal RP controls a ramp wave. A ramp wave is output when the ramp wave output signal RP is “H”. A step clock signal SCK equally divides the time period in which the ramp wave output signal RP is “H” into seven. A modulation voltage output signal MO controls a modulation reference voltage pulse. A modulation reference voltage pulse is applied to a modulation common voltage line 123 while the modulation voltage output signal MO is “H”. “CKD” refers to a data transfer clock signal as described above, and “DLS” refers to a data latch signal.
In the inorganic EL display device 1000, highly symmetrical AC pulses are applied to the light emitting layers in order to provide highly reliable display. In the first frame, a positive write voltage +(VW+VM) is applied; and in the second frame, a negative write voltage −VW is applied. As such, in the first frame, the amplitude of the modulation voltage needs to be lower as the luminance level is higher, and higher as the luminance level is lower. In the second frame, by contrast, the amplitude of the modulation voltage needs to be higher as the luminance level is higher, and lower as the luminance level is lower. In order to realize this, in the first frame, the display data signal which is input to the driving control circuit 101 is inverted and then is supplied to a data-side driving circuit 103. In the second frame, the display data signal is supplied to the data-side driving circuit 103 without being inverted. Display data signals DA0 through DA2 supplied to the data-side driving circuit 103 are generated by calculating an exclusive-OR of the display data signals D0 through D2 which are input to the driving control circuit 101 and the PN frame signal PNF.
The modulation voltage output signal MO generated by the driving control circuit 101 is supplied to a modulation power supply circuit 121 included in a modulation driving power supply circuit 102. The modulation power supply circuit 121 uses a DC/DC converter or the like to boost a driving circuit voltage VD (e.g., 12 V), which is externally input thereto, to a DC voltage having an amplitude VM (e.g., 35 V). Then, the modulation power supply circuit 121 converts the DC voltage to a modulation reference voltage pulse VMB in synchronization with the modulation voltage output signal MO. The modulation reference voltage pulse VMB obtained by the modulation power supply circuit 121 is output to the modulation common voltage line 123 as a modulation power supply voltage.
The ramp wave output signal RP generated by the driving control circuit 101 is supplied to a ramp wave generation circuit 122 included in the modulation driving power supply circuit 102. In synchronization with a rise of the ramp wave output signal RP, the ramp wave generation circuit 122 starts generating a ramp wave RVM having a peak amplitude VM (e.g., 35 V) from the driving circuit voltage VD. A generated ramp wave RVM is inclined such that the amplitude reaches the peak amplitude VM when the ramp wave output signal RP starts to fall. The ramp wave RVM is returned to a ground GND in synchronization with the fall of the ramp wave output signal RP. The ramp wave RVM generated by the ramp wave generation circuit 122 is output to a ramp wave line 124.
The display data signals DA0 through DA2, the ramp wave output signal RP, the modulation voltage output signal MO, the data transfer clock signal CKD, the data latch signal DLS, and the step clock signal SCK are supplied to a data-side control circuit 131 included in the data-side driving circuit 103. As shown in FIG. 2, the data-side control circuit 131 includes shift register and latch circuits 200 and amplitude control circuits 201. One shift register and latch circuit 200 and one amplitude control circuit 201 are provided for each of the data-side electrodes X1a, X1b, . . . Xna and Xnb.
The shift register latch circuit 200 receives the data transfer clock signal CKD, the data latch signal DLS, and the display data signals DA0 through DA2. As shown in FIG. 3, each shift register and latch circuit 200 includes three shift registers and three latches. Each shift register receives one of display data signals DA0 through DA2 at a D input terminal and receives a data transfer clock signal CKD at a CLK input terminal. The shift registers and the latches are connected to each other one by one. More specifically, a Q output terminal of a shift register is connected to a D input terminal of the latch. Each latch receives a data latch signal DLS at a CLK input terminal and is connected to the amplitude control circuits 201 (FIG. 2) at a Q output terminal. The Q output terminal of each shift register is also connected to a D input terminal of a shift register in the shift register and latch circuit 200 corresponding to the next data-side electrode.
In the shift register and latch circuits 200, the display data signals DA0 through DA2 (3 bits) are transferred to the respective shift registers in parallel, in synchronization with the data transfer clock CKD. After each horizontal period, data is latched in the latch by the data latch signal DLS. Thus, display data signals DA0(X) through DA2(X) are obtained. Here, (X) refers to one of X1a, X1b, X2a, . . . , Xna and Xnb.
The amplitude control circuit 201 receives the ramp wave output signal RP, the modulation voltage output signal MO and the step clock signal SCK which are generated by the driving control circuit 101, and the display data signals DA0(X) through DA2(X) from the shift register and latch circuits 200. As shown in FIG. 4, the amplitude control circuit 201 includes a counter circuit 220, a decoding circuit 221 and a mask circuit 222.
The counter circuit 220 includes seven flip-flop circuits. Each flip-flop circuit receives a step clock signal SCK at a CLK input terminal and receives a ramp wave output signal RP at a CLR terminal. A Q output terminal of one flip-flop circuit is connected to a D input terminal of the next flip-flop circuit. A /Q output terminal is connected to an input of a corresponding OR circuit. The OR circuits are included in the mask circuit 22. A D input terminal in the leftmost flip-flop circuit is connected to a supply voltage VCC. The counter circuit 220 receives the step clock signal SCK and the ramp wave output signal RP, and outputs signals having seven different pulse widths. The pulses rise at the /Q terminals of the flip-flop circuits at the same timing, and fall at different timings in synchronization with the rise of the step clock signal SCK. The pulse in one flip-flop circuit falls at a later time than the pulse in the flip-flop circuit to the left thereof.
The decoding circuit 221 includes a 3-bit-to-8-line decoder (corresponding to the standard logic 74137). The decoding circuit 221 receives the display data signals DA0(X) through DA2(X) from the shift register and latch circuit 200 respectively at select input terminals D, E and F, and thus outputs mask signals corresponding to the grades respectively from output terminals W0 through W7. Each mask signal is used for outputting only a signal having a necessary pulse width, among the signals having the seven different pulse widths output from the counter circuit 220, as an RP signal, and masking the other signals. The mask signals from the output terminals W0 through W6 are respectively output to one of two input terminals of the seven OR circuits included in the mask circuit 22. The mask signal from the output terminal W7 is output to one input terminal of an AND circuit 222a which is not connected to any output terminal of any OR circuit in the mask circuit 222.
The mask circuit 222 includes AND circuits and OR circuits. Among the signals having seven different pulse widths which are output from the counter circuit 220, a signal having a pulse width corresponding to one of the display data signals DA0(X) through DA2(X) is selected. An output from the mask circuit 222 is output to an AND circuit 201a connected to the mask circuit 222. The AND circuit 201a also receives the ramp wave output signal RP. Thus, an analog switch control signal MP for controlling a data-side driver 132 included in the data-side driving circuit 103 is generated.
As shown in FIG. 4, the amplitude control circuit 201 includes an other flip-flop circuit. A D input terminal of the flip-flop circuit is connected to the supply voltage VCC. The flip-flop circuit receives a signal obtained by inverting the modulation voltage output signal MO by an inverter at a CLK input terminal. A Q output terminal of the flip-flop circuit is connected to a CLR terminal thereof via three inverters connected in series. Thus, an output from the Q output terminal is received by the CLR terminal in an inverted state. The flip-flop circuit having such a structure generates a ramp wave discharging signal MD from the modulation voltage output signal MO.
The analog switch control signal MP and the ramp wave discharging signal MD which are generated by the amplitude control circuit 201 are supplied to the data-side driver 132. The modulation reference voltage pulse VMB and the ramp wave, which are generated by the modulation driving power supply circuit 102, are also supplied to the data-side driver 132.
As shown in FIG. 2, the data-side driver 132 includes an n-channel FET 300 and a p-channel FET 301 which are connected to each other via sources thereof. The FETs 300 and 301 are respectively connected in parallel to parasitic diodes 302 and 303, thus forming a source follower-type output element. The sources of the FETs 300 and 301 are connected to the data-side electrode X1a of the EL display panel 106. A drain of the n-channel FET 300 is connected to the modulation common voltage line 123, which is connected to the modulation driving power supply circuit 102 (FIG. 1). A drain of the p-channel FET 301 is connected to the ground GND. Gates of the FETs 300 and 301 are each connected to a gate capacitor 304 and are also connected to the ramp wave line 124 which is connected to the modulation driving power supply circuit 102 via an analog switch 305.
A gate of the analog switch 305 is controlled by the analog switch control signal MP which is output from the amplitude control circuit 201. When the analog switch 305 is made conductive by the analog switch control signal MP, the potential of the ramp wave is accumulated in the gate capacitor 304. The potential in the gate capacitor 304 is accumulated in the data-side electrode X1a as a modulation potential with no alternation. The analog switch control signal MP becomes “H” in a period corresponding to the driving frame and the grade, and the pulse width of the analog switch control signal MP is synchronized with the ramp wave and thus converted into a modulation voltage amplitude.
Tables 2-1 and 2-2 show the relationship between the display data signals D0 through D2 externally input to the inorganic EL display device 1000 and the amplitude level of the output modulation voltage in the first and second frames.
TABLE 2-1First frame (write voltage: positive)PNFD2D1D0Modulation driving voltageHHHH 0 VHHHL 5 V (1/7 VM)HHLH10 V (2/7 VM)HHLL15 V (3/7 VM)HLHH20 V (4/7 VM)HLHL25 V (5/7 VM)HLLH30 V (6/7 VM)HLLL35 V (7/7 VM)
TABLE 2-2Second frame (write voltage: negative)PNFD2D1D0Modulation driving voltageLHHH35 V (7/7 VM)LHHL30 V (6/7 VM)LHLH25 V (5/7 VM)LHLL20 V (4/7 VM)LLHH15 V (3/7 VM)LLHL10 V (2/7 VM)LLLH 5 V (1/7 VM)LLLL 0 V
In the first frame, a positive write voltage is applied to the scanning-side electrodes. Therefore, the amplitude of the modulation driving voltage applied to the data-side electrodes is lower as the luminance level is higher, and higher as the luminance level is lower. In the second frame, a negative write voltage is applied to the scanning-side electrodes. Therefore, the amplitude of the modulation driving voltage applied to the data-side electrodes is higher as the luminance level is higher, and lower as the luminance level is lower.
The data-side driver 132 further includes an n-channel FET 306 in parallel to the gate capacitor 304. A gate of the n-channel FET 306 is connected to the ramp wave discharging signal MD. The ramp wave discharging signal MD becomes “H” in a certain period in synchronization with the falling edge of the modulation voltage output signal MO. Then, the FET 306 becomes conductive, and the charge accumulated in the gate capacitor 304 is discharged.
The driving circuit voltage VD which is externally input to the inorganic EL display device 1000 using the DC/DC converter or the like is boosted to +(VW+VM) as a positive DC voltage and −VM as a negative DC voltage by a write power supply circuit 140 included in a write driving power supply circuit 104. The positive and negative DC voltages boosted by the write power supply circuit 140 are supplied to a write pulse generation circuit 141, and are converted into positive and negative pulse-like write voltages in accordance with the control signal supplied from the driving control circuit 101. In this case, “VW” is the light emitting threshold voltage VWa (180 V) of the light emitting layer A, and the driving circuit voltage VD is, for example, 12 V. The write driving power supply circuit 104 outputs 0 V for discharging the write voltage and is placed in a floating state for a period other than write and discharging.
The positive and negative pulse-like write voltages which are generated by the write driving power supply circuit 104 are supplied to a scanning-side driver 152 included in a scanning-side driving circuit 105, respectively via a pull-up line and a pull-down line (FIG. 1). As shown in FIG. 5, the scanning-side driving circuit 105 includes a plurality of switching circuits connected in parallel. The switching circuits are of a push-pull structure and each include a pull-up thyristor 153 and a pull-down thyristor 154. The pull-up line and the Q output terminal have a withstand voltage of about 250 V therebetween, and the Q output terminal and the pull-down line also have a withstand voltage of about 250 V therebetween. The electric potential difference between the pull-up line and the pull-down line changes within a range of about 5 V.
The scanning-side driver 152 is connected to a scanning-side control circuit 151. The scanning-side driver 152 is associated sequentially with the scanning-side electrodes Y1, Y2, . . . , Ym by shift registers (not shown) included in the scanning-side control circuit 151. All the scanning-side electrodes Y1, Y2, . . . , Ym are sequentially scanned. Since the ground potential of the scanning-side control circuit 151 is changed between a positive level and a negative level, the scanning-side control circuit 151 needs to be isolated from the driving control circuit 101. For this purpose, an isolation circuit 107 which includes a photocoupler or the like is provided between the scanning-side control circuit 151 and the driving control circuit 101. Thus, a control signal from the driving control circuit 101 is input to the scanning-side control circuit 151 where the control signal from the driving control circuit 101 and the scanning-side control circuit 151 are isolated from each other.
An exemplary method for driving the inorganic EL display device 1000 having the above-described structure will be described with reference to FIGS. 6A and 6B. In this example, the EL elements at the pixel C (FIG. 1) located at the intersections of the data-side electrodes X1a and X1b and the scanning-side electrode Y1, i.e., the EL elements (X1a, Y1) and (X1b, Y1) are caused to emit light at luminance level 6. The light emitting layer A is provided at the intersection of the data-side electrode X1a and the scanning-side electrode Y1, and the light emitting layer B is provided at the intersection of the data-side electrode X1b and the scanning-side electrode Y1. The light emitting layers A and B are supplied with the same level of voltage. FIGS. 6A and 6B show the waveforms of signals applied to the light emitting layer A. The waveforms of signals applied to the light emitting layer B are omitted.
In the first frame, an exclusive-OR of the display data signals D0 through D2 and the PN frame signal PNF, which are input to the driving control circuit 101, is calculated. As a result, the display data signals D0 through D2 are inverted so as to generate display data signals DA0 through DA2. The display data signals DA0 through DA2 are output to the data-side driving circuit 103.
The data-side driving circuit 103 receives the display data signals DA0 through DA2, the data transfer clock signal CKD, and the data latch signal DLS. The display data signals DA0 through DA2 are transferred to a prescribed position in the shift register and latch circuits 200 (FIG. 2) in the data-side control circuit 131 by the data transfer clock signal CKD. Then, the display data signals DA0 through DA2 are once latched at the rise of the data latch signal DLS. Thus, display data signals DA0(X) through DA2(X) are generated.
All the scanning-side electrodes Y1, Y2, . . . , Ym connected to the scanning-side driving circuit 105 are kept at the floating potential (substantially 0 V). The modulation common voltage line 123 receives the modulation reference voltage pulse VMB in accordance with the modulation voltage output signal MO. The data-side electrodes X1a, X1b, . . . , Xna and Xnb are each supplied with a modulation voltage of a desired level from the data-side driver 132 in accordance with the analog switch control signal MP and the ramp wave RVM. The analog switch control signal MP is obtained by processing the step clock signal SCK, the ramp wave output signal RP and the display data signals DA0(X) through DA2(X) by the data-side driving control circuit 131. The ramp wave RVM is supplied from the ramp wave line 124.
The data-side driver 132, which is connected to the data-side electrodes X1a and X1b corresponding to the EL elements (X1a, Y1) and (X1b, Y1) is charged until the gate capacitor 304 is charged to 1/7VM (5 V), the FET 300 is turned ON, and the data-side electrodes X1a and X1b are charged to 1/7VM (5 V).
Next, the pulse-like write driving voltage supplied from the write power supply circuit 104, i.e., +(VW+VM) (215 V) is supplied to the selected scanning-side electrode Y1 via the pull-up line and the selected pull-up thyristor 153 in the scanning-side driver 152. Thus, the scanning-side electrode Y1 is charged to +(VW+VM) (215 V).
Therefore, the voltage applied to both of two ends of the EL elements (X1a, Y1) and (X1b, Y1) is +VW+6/7VM (210 V). This value is obtained as a result of the write driving voltage and the modulation voltage being superimposed on each other. In this case, the EL element (X1a, Y1) is caused to emit light at luminance level 6, but the EL element (X1b, Y1) is caused to emit light only at about luminance level 4.
After the EL elements (X1a, Y1) and (X1b, Y1) emit light for a prescribed period of time, the scanning-side electrode Y1 is discharged to 0 V by the selected pull-down thyristor 154 via the pull-down line. The modulation voltage output signal MO becomes “L”, and thus the output of the modulation reference voltage VM to the modulation common voltage line 123 is stopped. The ramp wave charging signal MD becomes “H” for a prescribed period of time, and thus the FET 306 is turned ON so as to discharge the charge accumulated in the gate capacitor 304. Accordingly, the p-channel FET 301 is turned ON so as to discharge the charge accumulated in the EL elements (X1a, Y1) and (X1b, Y1).
Thus, driving of the selected scanning-side electrode Y1 is terminated. Until being driven in the second frame, the scanning-side electrode Y1 is in a floating state in which the scanning-side electrode Y1 is electrically isolated from the write driving power supply circuit 104. The scanning-side electrodes Y2 through Ym are sequentially driven in a similar manner. Thus, driving in the first frame is completed.
In the second frame, an exclusive-OR of the display data signals D0 through D2 and the PN frame signal PNF which are input to the driving control circuit 101 is calculated. As a result, the display data signals D0 through D2 are not inverted, and are output to the data-side driving circuit 103 as the display data signals DA0 through DA2.
The data-side driving circuit 103 receives the display data signals DA0 through DA2, the data transfer clock signal CKD, and the data latch signal DLS. The display data signals DA0 through DA2 are transferred to a prescribed position in the shift register and latch circuits 200 (FIG. 2) in the data-side control circuit 131 by the data transfer clock signal CKD. Then, the display data signals DA0 through DA2 are once latched at the rise of the data latch signal DLS. Thus, display data signals DA0(X) through DA2(X) are generated.
All the scanning-side electrodes Y1, Y2, . . . , Ym connected to the scanning-side driving circuit 105 are kept at the floating potential. The modulation common voltage line 123 receives the modulation reference voltage pulse VMB in accordance with the modulation voltage output signal MO. The data-side electrodes X1a, X1b, . . . , Xna and Xnb are each supplied with a modulation voltage of a desired level from the data-side driver 132 in accordance with the analog switch control signal MP and the ramp wave RVM. The analog switch control signal MP is obtained by processing the step clock signal SCK, the ramp wave output signal RP and the display data signals DA0(X) through DA2(X) by the data-side driving control circuit 131. The ramp wave RVM is supplied from the ramp wave line 124.
The data-side driver 132, which is connected to the data-side electrodes X1a and X1b corresponding to the EL elements (X1a, Y1) and (X1b, Y1) is charged until the gate capacitor 304 is charged to 6/7VM (30 V), the FET 300 is turned ON, and the data-side electrodes X1a and X1b are charged to 6/7VM (30 V).
Next, the pulse-like write driving voltage supplied from the write power supply circuit 104, i.e., −VW (−180 V) is supplied to the selected scanning-side electrode Y1 via the pull-down line and the selected pull-down thyristor 154 in the scanning-side driver 152. Thus, the scanning-side electrode Y1 is charged to −VW (−180 V).
Therefore, the voltage applied to both of two ends of the EL elements (X1a, Y1) and (X1b, Y1) is −(VW+6/7VM)(210 V). This value is obtained as a result of the write driving voltage and the modulation voltage being superimposed on each other. In this case, the EL element (X1a, Y1) is caused to emit light at luminance level 6, but the EL element (X1b, Y1) is caused to emit light only at about luminance level 4.
After the EL elements (X1a, Y1) and (X1b, Y1) emit light for a prescribed period of time, the scanning-side electrode Y1 is discharged to 0 V by the selected pull-up thyristor 153 via the pull-up line. The modulation voltage output signal MO becomes “L”, and thus the output of the modulation reference voltage VM to the modulation common voltage line 123 is stopped. The ramp wave charging signal MD becomes “H” for a prescribed period of time, and thus the FET 306 is turned ON so as to discharge the charge accumulated in the gate capacitor 304. Accordingly, the p-channel FET 301 is turned ON so as to discharge the charge accumulated in the EL elements (X1a, Y1) and (X1b, Y1).
Thus, driving of the selected scanning-side electrode Y1 is terminated. Until being driven in the first frame, the scanning-side electrode Y1 is in a floating state in which the scanning-side electrode Y1 is electrically isolated from the write driving power supply circuit 104. The scanning-side electrodes Y2 through Ym are sequentially driven in a similar manner. Thus, driving in the second frame is completed.
The conventional inorganic EL display device 1000 has the following problems.
In the conventional inorganic EL display device 1000 described above, the modulation voltage which is output from the data-side driving circuit 103 is output with a prescribed amplitude based on the display data signal. The relationship between the display data signal and the amplitude of the modulation voltage is the same in the light emitting layer of both of two display dots included in one pixel.
As shown in FIG. 7, in an inorganic EL element including a plurality of types of light emitting layers having different voltage vs. luminance characteristics, VW is set to the light emitting threshold voltage VWa (180 V) of the light emitting layer A, and VM is set to 35 V. Gray-scale display is performed by a voltage amplitude obtained by equally dividing the VM into seven. Accordingly, even a voltage which is optimum for the light emitting layer A only causes the light emitting layer B to emit light in the range of a non-emission level to a low luminance level. Thus, sufficient gray-scale display cannot be provided. In the case where the VW is set so as to provide optimum gray-scale display including a complete erasure state to a complete emission state to one of the light emitting layers, optimum gray-scale display cannot be provided to the other light emitting layer.
In the case where the VM is set to the difference (45 V) between the light emitting threshold voltage VWa (180 V) of the light emitting layer A and the light emitting saturation voltage VSb (225 V) of the light emitting layer B, a voltage amplitude obtained by simply equally dividing the voltage into seven is applied, the width between grades of a high luminance range is narrow with the light emitting layer A and the width between grades of a low luminance range is narrow with the light emitting layer B. Neither light emitting layer provides optimum gray-scale display.
In order to optimize the light emission state in an inorganic EL element display device including a plurality of types of light emitting layers having different voltage vs. luminance characteristics, Japanese Laid-Open Publication No. 10-39835 discloses a method for optimizing the pulse application time (pulse width) for each light emitting layer. However, an inorganic EL element is a capacitive element as can be appreciated from the structure thereof, and therefore is not suitable to a pulse width gray-scale method.
When a rectangular driving pulse is applied to an inorganic EL element, the current contributing to light emission steeply rises to a peak immediately after a rise of the voltage and behaves similarly to the current charging a capacitor. The current flows in a very short time of several microseconds. Therefore, even when the pulse width after the current flows is controlled, a sufficient luminance difference cannot be provided between grades. Accordingly, in order to provide gray-scale display having a sufficient luminance difference by controlling the pulse width, it is necessary to set a multi-stage pulse within several microseconds in which the charging current flows. However, even a slight change in the pulse width, caused by, for example, the response speed of the driving circuit or the control precision of the pulse width, significantly changes the luminance.
Optimum gray-scale display can be provided for all the light emitting layers by producing a plurality of types of light emitting layers having exactly the same voltage vs. luminance characteristic. It is very difficult to produce such inorganic EL elements with high reproducibility.